High voltage and high power integrated circuits in semiconductor-on-insulator (SOI) technologies often use a junction field effect transistor (JFET) in series with a conventional metal-oxide-semiconductor field effect transistor (MOSFET) as a replacement for a complex lateral double-diffused metal oxide semiconductor (LDMOS) transistor. This approach is simple, yet effective, and avoids costly technology additions to a complementary metal-oxide-semiconductor (CMOS) process flow.
CMOS circuits have been traditionally fabricated on silicon wafers having a single crystal orientation, ordinarily a (100) crystal orientation. Electrons have a higher mobility in silicon characterized by a (100) crystal orientation in comparison with silicon of a (110) crystal orientation. In contrast, holes have higher mobility in silicon characterized by a (110) crystal orientation in comparison with silicon of a (100) crystal orientation.
In recognition of the dependence of carrier mobility upon crystal orientation in single crystal silicon, hybrid orientation technology (HOT) has emerged to produce hybrid wafers based upon an SOI structure and characterized by device regions of different crystal orientations. Using such hybrid orientation technology wafers, CMOS circuits can be fabricated with nFETs formed in silicon device regions of a (100) crystal orientation and pFETs formed in silicon device regions of a (110) crystal orientation. Consequently, the performance of the different transistor types in CMOS circuits can be individually optimized.
Junction-type devices are readily implemented in CMOS technologies in HOT wafers. However, devices with vertical junction architectures are incompatible with advances in HOT technology that have downwardly scaled the thickness of the semiconductor layer in which the devices are manufactured. This design deficiency limits the continued implementation of vertical device structures in advanced HOT technologies.
What is needed, therefore, are advanced device structures for a junction field effect transistor fabricated using a hybrid orientation technology wafer, as well as advanced design structures for forming high voltage integrated circuits that include junction field effect transistors.